Field of the Invention
The invention relates to a circuit configuration for generating control signals for testing high-frequency synchronous digital circuits, especially memory chips.
The clock frequency of modern synchronous memory chips exceeds the signal frequency of tester systems currently used in production. To check the specification of memory chips which are in production, the “data mask” control signals must be generated at the maximum operating frequency of the memory chip for each group of data lines.
So that the memory chip does not have to be tested at a reduced clock frequency predetermined by the existing tester system and no new test systems must be acquired which are adapted to the high clock frequency, there is thus a demand for an inexpensive circuit configuration which is easy to implement and by which control signals for checking the specification of high-frequency synchronous digital circuits and especially of synchronous memory chips can be generated at a clock frequency which corresponds to the high-frequency clock period of the digital circuit to be checked and may be a multiple thereof.